Saturday, August 1, 2009

Analyse This

If one is foolish enough to try to design your own cpu, as I am, you might find yourself in need of a 'logic analyser'. I have a Mixed Signal Oscilloscope (MSO) from Bitscope. You can feed it data from a bus and it has programable logic triggers, however it has only a small amount of memory.

Now the problem is that the bus activity is sampled at n rate, basically polled. So one has to juggle the sample rate to get the largest capture without 'missing' an event.
Now I might be missing something here, but what I want is an analyser that latches the bus whenever there is a change on selected lines. My device needs a fast clock, so that when the bus is latched the state is saved with a timestamp to memory. If we use a 32 bit clock we need to save 5 bytes per event. That's 5 bytes only when something happens. The replay is the state in a timeline - easily displayed in multiple formats. So instead of saving multiple copies of the bus because of oversampling, we are now saving only the state changes using an interupt model.

This can't be a novel approach, yet I can't seem to find an instrument that works this way.
If anyone knows something I don't (nearly everyone) feel free to comment, before I get to far into building my own.

This thing looks interesting.
Perhaps with super speed and stacks of memory it might be a case of who cares.


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